Pipelining is a technique for increasing the effective throughput of a digital computer by stacking up a series of instructions for rapid sequential execution. This is accomplished through the use of serial registers which hold the various instructions in a state of readiness. Time saving results from the instant availability of the next instruction to be executed as opposed to the slower alternative technique of accessing memory for a fresh instruction after the previous instruction has been executed.
Effective pipelining requires anticipation of instructions before they are actually commanded by the program. This is done by means of a sequencer or counter which simply increments the address of the current instruction on the assumption that the most likely next instruction is that having the next address in a numerical sequence. Thus when a jump or branch instruction occurs, some means must be provided to prevent execution of the sequential instructions which have been generated and to substitute the instructions which correspond to the new sequence.
The use of pipelining in a digital computer is described in "VLSI Shakes the Foundation of Computer Architecture" Electronics, May 24, 1979, pp 111-133. That article describes a technique utilizing parallel pipelines, one of which carries the current instructions and the others of which carry the most likely branch instructions. When a branch instruction occurs, the computer simply switches to the pipeline containing the new routine. This technique obviously increases the hardware requirements of the computer for both the parallel pipelines and the control circuitry for the selection thereof.